CMOS semiconductor manufacturing technologies are relatively inexpensive, and permit the design of integrated circuits including both digital and analog functions. CMOS technology has been used to build multi-stage differential amplification circuits for analog-to-digital converters. Such circuits have employed offset memorization to compensate for input offset voltages in the amplification stages.
Offset memorization is generally performed by dividing circuit operation into two phases, an offset memorization phase and an amplification phase. During the offset memorization phase, a capacitor in series with the output of an amplification stage is grounded, allowing the stage's input offset voltage multiplied by the stage's gain to be stored in the capacitor. During the subsequent amplification phase, the memorized offset voltage cancels by subtraction the actual offset voltage of the amplification stage. Alternatively, offsets can be memorized by providing a feedback path around an amplification stage during the offset memorization phase.
Different CMOS differential amplification stages have been proposed for these analog-to-digital conversion applications. These stages have not been particularly well suited to low-voltage operation, however, because too many transistors are connected between the supply rails or because resistors are used to load the outputs of the gain stages.